The subject matter of the teachings disclosed herein relates to a method of forming back-end-of-line (BEOL) trench and via dual damascene features associated with the manufacture of integrated circuits. More particularly, the subject matter of the teachings disclosed herein relates to a method of forming small geometry dual damascene features that uses tri-layer resist, eliminates resist poisoning and minimizes ultra low-k damage due to etch and ash processes.
The integrated circuit (IC) industry has seen enormous performance improvements and miniaturization in the past few decades through scaling of IC feature sizes. A primary contribution to the IC performance improvement has come from the device gate level. However, as device scaling continues into the deep submicron region, metal interconnects become the bottleneck for continued IC performance improvement. The gain in device speed at the gate level is offset by propagation delays at the metal interconnect due to the increased RC time constant. The RC time delay can be reduced by the incorporation of low dielectric constant (k) materials and/or high conductivity metals. The use of low-k dielectric materials also lowers power consumption and reduces crosstalk.
Continuous scaling of devices will require the use of ultra low-k (ULK) materials. Incorporation of air into dense materials to make them porous is an attractive method to obtain ULK materials. With the introduction of ULK materials (e.g., k<2.5) to the 45 nm technology node, a new challenge comes from ULK film damage due to etch and ash processes. The ULK sidewall damage observed can be as high as 20-30 nm per side of trench or via features. This is a significant issue in meeting the 45 nm trench or via specifications (<2 nm per side). Minimizing the exposure of ULK film to ash and etch processes is required to reduce the ULK damage.
A significant obstacle in Cu/low-k (or ULK) dual damascene via and trench patterning is resist pattern defects or resist poisoning. Resist poisoning occurs due to an interaction between a deep ultraviolet (DUV) resist and low-k/ULK films or etch-stop films (such as silicon nitride or silicon carbide). An integration scheme that eliminates poisoning is required.
A conventional dual hardmask integration uses a trench-first scheme with single-layer resist for via and trench patterning. However, the trench-first dual hardmask scheme has issues with resist thinning and issues with depth of focus during subsequent via trench patterning due to the relatively large trench open area.
For the 45 nm technology and beyond, one of the biggest challenges is to provide minimum pitch resolution and decent depth of focus (DOF) through all the pattern pitches during photolithography. Due to resist collapse and scumming concern, resist thickness needs to be reduced to 150 nm or less for the 45 nm technology node. The 150 nm thick resist cannot provide sufficient mask protection during trench and via etch. Therefore, an additional robust mask layer is required. A metal hardmask is one of the options to improve hardmask selectivity. However, a dielectric hardmask scheme is preferred over a metal hardmask scheme since it eliminates the need for separate metal deposition and etch tools.
A tri-layer stack with resist on top of an SOG (spin-on glass) layer (developer-resistant hardmask layer) and an organic underlayer (planarizing layer) at the bottom is used to replace the conventional resist/BARC stack in order to provide good reflectivity control for lithography and a usable hardmask for etch. Once the top resist is patterned, the image can be transferred to the SOG layer through oxide (SOG) etch, and the remaining SOG serves as the hardmask to etch the organic underlayer. Then the thick underlayer is used as a mask for the low-k or ULK dielectric etch to form trench or via features.
Accordingly, the present teachings solve these and other problems related to resist poisoning and damage of ultra low-k materials by providing a via-first scheme with dual dielectric hardmask and tri-layer resist.